Isolated tri-gate transistor fabricated on bulk substrate

ABSTRACT

A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

BACKGROUND

In the manufacture of integrated circuit devices, multi-gatetransistors, such as tri-gate transistors, have become more prevalent asdevice dimensions continue to scale down. In conventional processes,tri-gate transistors are generally fabricated on either bulk siliconsubstrates or silicon-on-insulator substrates. In some instances, bulksilicon substrates are preferred due to their lower cost and becausethey enable a less complicated tri-gate fabrication process. In otherinstances, silicon-on-insulator substrates are preferred because of theimproved short-channel behavior of tri-gate transistors.

On bulk silicon substrates, the fabrication process for tri-gatetransistors often encounters problems when aligning the bottom of themetal gate electrode with the source and drain extension tips at thebottom of the transistor body (i.e., the “fin”). When the tri-gatetransistor is formed on a bulk substrate, proper alignment is needed foroptimal gate control and to reduce short-channel effects. For instance,if the source and drain extension tips are deeper than the metal gateelectrode, punch-through may occur. Alternately, if the metal gateelectrode is deeper than the source and drain extension tips, the resultmay be an unwanted gate cap parasitic.

Accordingly, there is a need for a tri-gate transistor fabricationprocess that combines the ease of fabrication provided by bulksubstrates with the improved short channel effects provided bysilicon-on-insulator substrates.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional tri-gate device.

FIG. 2 is a method of forming an isolated semiconductor body inaccordance with an implementation of the invention.

FIGS. 3 to 10 illustrate structures formed when the process of FIG. 2 iscarried out.

FIG. 11 is a method of forming an isolated semiconductor body inaccordance with another implementation of the invention.

FIGS. 12 to 14 illustrate structures formed when the process of FIG. 11is carried out.

DETAILED DESCRIPTION

Described herein are systems and methods of fabricating a tri-gatetransistor on a bulk semiconductor substrate with improved short channeleffects. In the following description, various aspects of theillustrative implementations will be described using terms commonlyemployed by those skilled in the art to convey the substance of theirwork to others skilled in the art. However, it will be apparent to thoseskilled in the art that the present invention may be practiced with onlysome of the described aspects. For purposes of explanation, specificnumbers, materials and configurations are set forth in order to providea thorough understanding of the illustrative implementations. However,it will be apparent to one skilled in the art that the present inventionmay be practiced without the specific details. In other instances,well-known features are omitted or simplified in order not to obscurethe illustrative implementations.

Various operations will be described as multiple discrete operations, inturn, in a manner that is most helpful in understanding the presentinvention, however, the order of description should not be construed toimply that these operations are necessarily order dependent. Inparticular, these operations need not be performed in the order ofpresentation.

Implementations of the invention provide a fabrication process for atri-gate transistor on a bulk semiconductor substrate where the tri-gatetransistor is fully isolated, thereby combining the simple tri-gate onbulk process with the better short-channel behavior of tri-gate onsilicon-on-insulator. In accordance with an implementation of theinvention, a semiconductor body for the tri-gate transistor is formedout of the bulk substrate. This semiconductor body is often referred toas the “fin” of a tri-gate transistor. Next, an oxide layer isfabricated beneath the semiconductor body using an oxidation process.The oxide layer isolates the semiconductor body from the bulk substrateand reduces junction capacitance.

For reference, FIG. 1 illustrates a conventional tri-gate transistor100. As shown, the tri-gate transistor 100 is formed on a bulksemiconductor substrate 102, such as a bulk silicon substrate. Thetri-gate transistor 100 includes a semiconductor body 104, also known asthe fin structure of the tri-gate transistor 100. The semiconductor body104 is generally formed from the same material as the bulk substrate102. The tri-gate transistor 100 also includes a metal gate electrode106 formed from a conductive material such as polysilicon or a metal. Asshown, the metal gate electrode 106 is adjacent to three separatesurfaces of the semiconductor body 104, thereby forming three separategates for the transistor.

A source region 104A and a drain region 104B are formed in thesemiconductor body 104 on opposite sides of the metal gate electrode106. A channel region (not labeled) is formed in the semiconductor body104 between the source and drain regions 104A/B and below the metal gateelectrode 106. As is known in the art, source and drain tip extensions(not shown) may be formed in the channel region. Since the semiconductorbody 104 is not isolated from the substrate 102, at interface 108,alignment of the bottom of the tip extensions with the bottom of themetal gate electrode 106 is critical. If the tip extensions penetratedown into the substrate 102, or if the tip extensions do not penetrateto the bottom of the semiconductor body 104, short-channel effect issuesmay arise.

FIG. 2 is a method 200 of forming an isolated semiconductor body on abulk substrate in accordance with an implementation of the invention.FIGS. 3 through 10 illustrate cross-sections of structures that areformed when the method 200 is carried out.

The method 200 begins by providing a bulk substrate upon which theisolated semiconductor body of the invention may be formed (202 of FIG.2). In implementations of the invention, the bulk substrate may beformed from silicon or a silicon alloy. In further implementations, thebulk substrate may include materials such as germanium, indiumantimonide, lead telluride, indium arsenide, indium phosphide, galliumarsenide, or gallium antimonide, any of which may be combined withsilicon.

The bulk substrate includes a hard mask layer formed from a materialsuch as silicon nitride (e.g., Si₃N₄). The silicon nitride hard masklayer may be formed using conventional processes, such as a chemicalvapor deposition process on a top surface of the silicon bulk substrate.FIG. 3 illustrates a cross-section of a bulk substrate 300 that includesa silicon nitride layer 302 formed on its top surface.

The hard mask layer may be etched to form a patterned hard mask layer(204). Conventional processes known in the art may be used to patternthe hard mask layer, such as conventional lithography processes using adry etch or a reactive ion etch in plasmas of CHF₃, CH₃F, or CF₄. Infurther implementations, other wet or dry etching processes may be used.The patterned hard mask layer may then be used as a mask to pattern thebulk substrate to form a fin structure (206). Conventional processesknown in the art may be used to pattern the bulk substrate, such as awet etching process using NH₄OH or a dry etching process using HBrCl.Again, in further implementations, other wet or dry etching processesmay be used. This fin structure may be used to form a semiconductorbody. FIG. 4 illustrates a cross-section of a patterned hard maskstructure 302A on the bulk substrate 300. FIG. 5 illustrates across-section of a fin structure 500 that has been formed by etching thebulk substrate 300 using the patterned hard mask structure 302A as amask.

Next, a shallow trench isolation (STI) material is deposited around thefin structure (208). In various implementations of the invention, theSTI material may be an insulating material, such as a dielectricmaterial or another oxide material. In some implementations, silicondioxide or SiOF may be used as the STI material. The STI material may bedeposited using conventional deposition processes, such as chemicalvapor deposition (CVD), physical vapor deposition (PVD), and atomiclayer deposition (ALD). FIG. 6 illustrates a cross-section of an STImaterial 600 that has been deposited adjacent to the fin structure 500.

The STI material is then recessed to expose a portion of the finstructure (210). The exposed portion of the fin structure willeventually become an isolated semiconductor body for use in a tri-gatedevice. Accordingly, the degree or depth to which the STI material isrecessed and the fin structure is exposed corresponds to a desiredthickness or height of the isolated semiconductor body being formed.Conventional processes may be used to recess or etch the STI material,including but not limited to wet etching processes using hydrogenfluoride (HF) or dry etching processes using CHF₃, CH₃F, or CF₄. Infurther implementations, other wet or dry etching processes may be used.FIG. 7 illustrates a cross-section of the STI material 600 after it hasbeen recessed, thereby exposing a portion of the fin structure 500.

Next, a protective nitride cap is formed over the exposed portion of thefin structure 500 (212). The previously exposed portions of the finstructure are now contained within the nitride cap and protected fromoxidation. The nitride cap may be formed of the same material as thehard mask material, such as silicon nitride (e.g., Si₃N₄), and may beformed using conventional processes. For instance, a deposition processsuch as CVD, PVD, or ALD may be used with precursors such as silane andammonia to form a nitride layer over the STI material and the finstructure. An etching process, such as those described above, may thenbe used to etch the nitride layer and form a nitride cap over the finstructure. FIG. 8 illustrates a cross-section of a nitride cap 800formed on the fin structure 500.

In accordance with implementations of the invention, a thermal oxidationprocess is now carried out to oxidize a portion of the fin structurethat is just below but not contained within the nitride cap (214). Inother words, the oxidation process consumes an unprotected portion ofthe silicon fin that is below the bottom edge of the nitride cap,thereby converting the silicon into a silicon oxide material. Theportion of the fin structure protected by the nitride cap now becomesisolated from the bulk substrate by this newly formed silicon oxide. Inimplementations of the invention, the thermal oxidation process may becarried out by annealing the substrate at a temperature between around900° C. and around 1100° C. for a time duration between around 0.5 hoursand around 3 hours or more. The thermal oxidation may take place in anatmosphere that contains one or more of O₂, H₂O, steam, and HCl.

FIG. 9 illustrates a cross-section of the fin structure 500 after aportion of the silicon has been consumed by the thermal oxidationprocess. As shown, the portion of the fin structure 500 protected by thenitride cap 800 now forms an isolated semiconductor body 900. Thematerial directly below the isolated semiconductor body 900 is an oxidelayer, generally a silicon dioxide layer, formed during the thermaloxidation process.

The nitride cap may be removed from the isolated semiconductor bodyafter the thermal oxidation process (216). Conventional processes forremoving a nitride from silicon may be used, such as the conventionalwet or dry etching processes detailed above. In some implementations, awet etch process using phosphoric acid may be used since it has a highselectivity to both oxides and silicon. The isolated semiconductor body900 may now be used to form a tri-gate transistor with improvedshort-channel effects relative to conventional tri-gate transistorsformed on bulk silicon.

FIG. 10 illustrates isolated semiconductor body 900 after the nitridecap 800 is removed. The semiconductor body 900 is isolated from the bulksubstrate 300 and may now be used as a semiconductor body for a tri-gatetransistor. Conventional tri-gate fabrication processes may be used fromthis point forward.

FIG. 11 is an alternate method 1100 of forming an isolated semiconductorbody in accordance with an implementation of the invention. The method1100 follows the same process as the method 200 until the nitride cap isformed (i.e., the method 1100 includes the processes 202 through 212 ofFIG. 2).

Once the nitride cap is formed, a second recess of the STI material isperformed (1102 of method 1100). In this implementation, the STImaterial is recessed a second time to expose a portion of the finstructure below the nitride cap that will be converted into an oxide.Accordingly, the degree to which the STI material is recessed here willdepend on the desired thickness of oxide layer being formed to isolatethe semiconductor body. A wet etch process using hydrofluoric acid or abuffered oxide wet etch may be used to recess the STI material. FIG. 12illustrates a cross-section of the STI material 600 after it has beenrecessed second time, thereby exposing a portion of the fin structure500 below the nitride cap 800.

In accordance with implementations of the invention, a thermal oxidationprocess is now carried out to oxidize the portion of the fin structurethat was exposed during the second STI recess (1104). The oxidationprocess consumes the silicon that is exposed and not protected by thenitride cap, converting the silicon into a silicon oxide material. Here,the thermal oxidation process has a faster oxidation rate on the siliconbecause the silicon is exposed, yielding a relatively thinner and bettercontrolled oxide. The portion of the fin structure protected by thenitride cap now becomes isolated from the bulk substrate by this newlyformed silicon oxide. As described above, the thermal oxidation processmay be carried out by annealing the substrate at a temperature betweenaround 900° C. and around 1100° C. for a time duration between around0.5 hours and around 3 hours or more. The thermal oxidation may takeplace in an atmosphere that contains one or more of O₂, H₂O, steam, andHCl.

FIG. 13 illustrates a cross-section of the fin structure 500 after theexposed portion of the silicon has been consumed by the thermaloxidation process to form an oxide layer 1300. As shown, the portion ofthe fin structure 500 protected by the nitride cap 800 now forms anisolated semiconductor body 900. The material directly below theisolated semiconductor body 900 is the oxide layer 1300, generally asilicon dioxide layer, formed during the thermal oxidation process.

The nitride cap may now be removed from the isolated semiconductor bodyafter the thermal oxidation process (1106). Conventional processes forremoving a nitride from silicon may be used, as described above. Theisolated semiconductor body 900 may now be used to form a tri-gatetransistor with improved short-channel effects relative to conventionaltri-gate transistors formed on bulk silicon. FIG. 14 illustrates theisolated semiconductor body 900 after the nitride cap 800 is removed.Once again, conventional tri-gate fabrication processes may be used fromthis point forward.

Accordingly, methods of forming an isolated semiconductor body on a bulksubstrate have been described. In accordance with implementations of theinvention, the formation of an oxide layer beneath the semiconductorbody provides self alignment of the gate and source/drain tip extensionsfor optimal gate control. Additional benefits include a simplificationof engineering required for the source and drain tip extensions, areduction of source and drain junction capacitance, and the creation ofa relatively thin isolation layer under the active tri-gate device,which provides improved short-channel immunity relative to standardsilicon-on-insulator devices that use a relatively thick isolationlayer. In addition, the fully isolated semiconductor body of theinvention enables other silicon-on-insulator type applications, such asa single device memory with a floating body, even though the startingwafer is bulk silicon.

The above description of illustrated implementations of the invention,including what is described in the Abstract, is not intended to beexhaustive or to limit the invention to the precise forms disclosed.While specific implementations of, and examples for, the invention aredescribed herein for illustrative purposes, various equivalentmodifications are possible within the scope of the invention, as thoseskilled in the relevant art will recognize.

These modifications may be made to the invention in light of the abovedetailed description. The terms used in the following claims should notbe construed to limit the invention to the specific implementationsdisclosed in the specification and the claims. Rather, the scope of theinvention is to be determined entirely by the following claims, whichare to be construed in accordance with established doctrines of claiminterpretation.

1. A method of forming an isolated semiconductor body comprising:patterning a bulk substrate to form a fin structure; depositing aninsulating material around the fin structure; recessing the insulatingmaterial to expose a portion of the fin structure; depositing a nitridecap over the exposed portion of the fin structure to protect the exposedportion of the fin structure; carrying out a thermal oxidation processto oxidize an unprotected portion of the fin structure below the nitridecap, thereby isolating the protected portion of the fin structure fromthe bulk substrate; and removing the nitride cap.
 2. The method of claim1, wherein the depositing of the insulating material comprisesdepositing silicon dioxide using a process selected from the groupconsisting of epitaxial growth, CVD, PVD, and ALD.
 3. The method ofclaim 1, wherein a depth that the insulating material is recessedcorresponds to a desired height of the isolated semiconductor body. 4.The method of claim 1, wherein the nitride cap comprises siliconnitride.
 5. The method of claim 1, wherein the thermal oxidation processcomprises annealing the substrate at a temperature between around 900°C. and around 1100° C. for a time duration between around 0.5 hours andaround 3 hours.
 6. The method of claim 1, wherein the bulk substratecomprises a bulk silicon substrate.
 7. The method of claim 1, whereinthe recessing of the insulating material comprises using an etchingprocess to remove a portion of the insulating material.
 8. A method offorming an isolated semiconductor body comprising: patterning a bulksubstrate to form a fin structure; depositing an insulating materialaround the fin structure; recessing the insulating material a first timeto expose a first portion of the fin structure; depositing a protectivenitride cap over the first portion of the fin structure; recessing theinsulating material a second time to expose a second portion of the finstructure below the protective nitride cap; thermally oxidizing thesecond portion of the fin structure, thereby isolating the first portionof the fin structure from the bulk substrate; and removing the nitridecap.
 9. The method of claim 8, wherein the depositing of the insulatingmaterial comprises depositing silicon dioxide using a process selectedfrom the group consisting of epitaxial growth, CVD, PVD, and ALD. 10.The method of claim 8, wherein a depth that the insulating material isrecessed the first time corresponds to a desired height of the isolatedsemiconductor body.
 11. The method of claim 8, wherein the nitride capcomprises silicon nitride.
 12. The method of claim 8, wherein thethermal oxidation process comprises annealing the substrate at atemperature between around 900° C. and around 1100° C. for a timeduration between around 0.5 hours and around 3 hours.
 13. The method ofclaim 8, wherein the bulk substrate comprises a bulk silicon substrate.14. An apparatus comprising: a bulk substrate; a semiconductor bodyformed by patterning a fin structure from the bulk substrate; and anoxide layer isolating the semiconductor body from the bulk substrate,wherein the oxide layer is formed by thermally oxidizing a portion ofthe fin structure patterned from the bulk substrate.
 15. The apparatusof claim 14, wherein the bulk substrate and the semiconductor body areformed from the same material.
 16. The apparatus of claim 15, whereinthe material comprises silicon.
 17. The apparatus of claim 15, whereinthe material comprises silicon alloyed with a second material selectedfrom the group consisting of germanium, indium antimonide, leadtelluride, indium arsenide, indium phosphide, gallium arsenide, andgallium antimonide.
 18. The apparatus of claim 14, wherein the oxidelayer comprises silicon dioxide.